1. Field of the Invention
The present invention relates to a semiconductor device production method and a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, in particular, integrated circuits that use MOS transistors, continues to increase. With the increase in the degree of integration, MOS transistors used in the circuits have been miniaturized to a nanometer scale. With miniaturization of MOS transistors, issues have arisen in that reducing leakage current has become difficult and decreasing the area occupied by circuits has become difficult due to need of securing the required amount of current. In order to address these issues, a surrounding gate transistor (hereinafter referred to as an “SGT”) has been proposed in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer (for example, refer to Japanese Unexamined Patent Application Publication No. 2-71556, Japanese Unexamined Patent Application Publication No. 2-188966, and Japanese Unexamined Patent Application Publication No. 3-145761).
According to an SGT production method of related art, a silicon pillar with a pillar-shaped nitride film hard mask is formed, a diffusion layer is formed below the silicon pillar, and then a gate material is deposited. Subsequently, the gate material is planarized and etched back to form an insulating film side wall on side walls of the silicon pillar and the nitride film hard mask. Then a resist pattern for a gate line is formed, the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed in an upper portion of the silicon pillar so as to produce an SGT (for example, refer to Japanese Unexamined Patent Application Publication No. 2009-182317).
As the distance between adjacent silicon pillars decreases, it becomes necessary to deposit a thick gate material between such silicon pillars and very small holes called voids are sometimes formed between the silicon pillars according to the above-mentioned method. If such voids are formed, holes are formed in the gate material after etch back. If an insulating film is subsequently deposited between the silicon pillars to form an insulating film side wall, the insulating film is deposited in the voids as well. Accordingly, it becomes difficult to process the gate material that lies between silicon pillars.
To address this, a technique that involves the following has been disclosed (for example, refer to B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. D. Lo, and D. L. Kwong, “Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET”, IEEE Electron Device Letters, VOL. 29, No. 7, July 2008, pp 791-794): A gate oxide film is formed after formation of a silicon pillar. After a thin polysilicon is deposited, a resist for forming a gate line covering an upper portion of the silicon pillar is formed. The gate line is etched, a thick oxide film is deposited, an upper portion of the silicon pillar is exposed, and a thin polysilicon on the upper portion of the silicon pillar is removed. Lastly, the thick oxide film is removed by wet etching.
However, according to the related art, a technique that uses metal in gate electrodes is not demonstrated. Moreover, formation of a resist is necessary to form a gate line that covers the upper portion of the silicon pillar; since the resist covers the upper portion of the silicon pillar, the process is not a self-aligned process.